Memory Layout Engineer

Job description

## About the role SmartSoC Solutions is seeking a Memory Layout Engineer to join its semiconductor team in Bangalore. The role focuses on designing and integrating memory layouts for advanced technology nodes, contributing to cutting‑edge semiconductor products. ## Key responsibilities - Design memory layouts for building blocks such as Bit Cell Arrays, Row/Column Decoders, Sense Amplifiers, and I/O blocks. - Integrate top‑level memory layouts and perform physical verification using DRC and LVS. - Ensure layouts meet Design for Manufacturability (DFM) and Design for Yield (DFY) requirements. - Analyse power and signal integrity of layouts. - Develop and maintain automation scripts (PERL, Shell, TCL, or SKILL). ## Required qualifications - 4+ years of hands‑on experience in memory layout for advanced nodes (2nm/3nm/5nm). - Strong knowledge of TSMC or comparable process technologies. - Solid understanding of physical verification, layout methodologies, and semiconductor design flows. - Scripting proficiency is a plus. ## Benefits & culture - Work on next‑generation semiconductor technologies. - Collaborative environment with a focus on innovation. - Opportunities for professional growth within a fast‑growing company. - Competitive compensation and comprehensive benefits package.

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Compensation

Salary for this role is not disclosed by the employer. We don’t have enough benchmark data from similar roles to produce a reliable estimate. The actual compensation will be discussed during the interview process.